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Compilation and Architecture support to mitigate fault and side-channel attacks to modern microprocessors (2016 - present)
The project aims to leverage a synergy betwen high-performance architetures, parallelizing compilers and computer security to provide hardware software co-design directions and automation in the deployment of mitigation against fault and side-channel attacks. The rational behind this project is that existing, sound techniques from the high-performance computing domain can be re-purposed/architected under the light of sound threat models. The advantage of doings so, beyond leveraging a solid body of literature, is to setup single mitigations against multiple threats, to promote sound composibility of security properties and attack mitigation, as well as, to loosen the trade-off between performance and security mitigation. Notable examples, are the use of vectorization for introducing resistance againt DPA and fault-attacks to modern micro processors, and the use of value prediction to mitigate fault attacks.
The project was kindly supported by Qualcomm Technologies Inc. 

Domain Specific Programmable Architecture for Lattice-based Cryptography Schemes (2016 - present)
The project aims to provides analysis, hardware co-design and hints to the semiconductor industry for early adoption of post-quantum cryptography schemes in hardware. Our analysis includes both compiler and micro-architectural optimization aspects. The specific focus of the project is on lattice-based cryptography, is due to the fact that these schemes provide foundational security properties, ease of implementation and find applications to both traditional and emerging security
problems such as encryption (asymmetric, but also symmetric), digital signature, key exchange, homomorphic encryption etc.
Lattice-based schemes require significant computational resources, making their realization in varying scenarios (e.g., from high-performance servers to resource constrained IoT) challenging. Furthermore,
since these schemes are yet to be standardized, there is a critical need for agile deployment in the face of emerging and changing standards. The project tackles both these issues (computational pressure and agile deployment) by deploying programmable accelerators with specialized datapath and controllers that can achieve improved performance and energy efficiency. 
We developed a design flow and with it we developed a multitude of domain specific processors to accomodate the largest pool of lattice-based cryptography schemes, including NewHope, Dilithium, Kyber, etc.  
The project received supporting funding from Qualcomm Technologies, Inc.

Feature-agnostic learning of computing system performance optimizations (2014 - present)
This project aims to introduce methodologies for program characterization and its application to computing performance problems (e.g., hardware procurement, performance modeling/ prediction, automatic performance test generation, compiler and run-time optimization tuning) that abstract from the traditional feature engineering approach widely used in machine learning aided compilation/run-time. 
To this end, the project leverages datasets perfomance measurements to identify algorithmic and system level optimization solutions that can maximize application performance, and uses modern machine learning recommender systems to finding optimized solutions - via low-rank matrix factorization.
This project was kindly supported by Qualcomm Technologies, Inc.

Corner cases software optimization in the polyhedral model (2015 - 2018)
This project aims to apply polyhedral optimization to the case of fused layers in artificial neural networks, for different target architectures. It does study the problem of polyhedral optimization for the targeted workloads at different levels of abstractions, including source-to-source and IR-to-IR. 


WebRTCBench (2012 - 2013)
This project provided a benchmark for Web Real Time Communication, to profile critical portion of the software architecture and provide hints to its mapping on modern micro-architectures. The project was Kindly funded by Intel Corporation.
The benchmark is available at the following link: https://github.com/ucisysarch/WebRTCBench